1. Field
This disclosure relates generally to semiconductors, and more specifically, to semiconductor data storage devices and methods of data storage.
2. Related Art
A category of semiconductor memories has two or more input/output (I/O) terminals or ports and is known as a multiple port (multi-port) memory. Memories are typically implemented in arrays of intersecting columns and rows. A memory storage circuit for storing a single data bit is provided at each intersection. When data from two or more of the ports is to be written to the memory at the same time, several problems exist. In particular, if two or more write word lines in a memory array are enabled by two or more separate port inputs to write to the same memory cell, the data being coupled from each port may have an opposite bit value and create an indeterminate or incorrect data value at the input of the memory cell. Additionally, this data contention event consumes additional power and is inefficient. Further, the continual switching of the bit line enabling transistors when higher power is being consumed is detrimental to the integrity of the bit line enabling transistors. In particular, the gate oxides of the transistors are modified by higher current flow and exhibit different electrical parameters.
Others have recognized the detrimental effects of data write contentions in a multiple port memory. A proposed solution to avoid the concurrent writing of data to a same memory cell from differing memory ports is to use comparators in the addressing decoding circuitry to compare addresses from each port with all other ports. If the same address from different ports is detected, a determination is made as to which address to permit and all others are serviced later. This determination is typically made by using an arbitration logic circuit that arbitrates which address should be permitted to write to the memory cell. Thus, an address collision is detected prior to performing a write access. When multiple port memories are implemented, a large number of comparison operations must be implemented. In addition to the size and power that is consumed by this circuitry, the comparison operations represent a significant amount of a memory cycle as measured by contemporary memory clocking speeds. Thus the known multi-port memories frequently are slowed by the address decoding circuitry functioning to detect data write contentions to a same memory cell.